Recon-0 platform

After the previous post, I thought maybe we should have a collection of different flavours of NIOSII system, so that new comers can jump on board quickly, download the configuration file and start to do interesting things straight away. So I’ve created a “Recon” project hosted on github.

I hope that the repository would be built up by community and become a rich collection of architectures. New users who are not so familiar with FPGA can have some starting points and quickly turn their FPGA development kit into micro controller kit and start doing cool things.

I envision that the target audience would be

  1. Someone who is familiar with C/C++ development but the conventional microcontroller kits such as Arduino/PIC/AVR are not flexible/powerful enough for them. This maker then can get a small FPGA kit, download a suitable architecture from the repository and then customize it to suit her own project.
  2. Someone who are familiar with C/C++/AVR development and want to start learning VHDL/Verilog. My experience shows that, interesting products often include customized FPGA fabric, but at the center of the system is still a microcontroller core.
  3. Makers who just want to quickly bring things together and prototype their ideas.

The advantage of having a common repository is that the hardware part is done and reused. The difficult part of doing FPGA embedded system is setting up of the hardware, making connections, verifying timing.

I named the very first architecture in the collection RECON-Zero and it’s designed to run on  Altera’s MAX10 devices, at least 10M04 – 4K LUT+Flops.

In this architecture, you have a flash memory controller that uses the MAX10 Altera FPGA on chip flash. 2 RAMs that are intended to be used for code and ISR routines. The RECON-IO and RECON-Timer are written by me. I think these 2 components are simple but very important in hobbyists projects. Recon timer implements 2 x 32-bit timers, one increments every 1 millisecond, the other increments every second. The timer can be programmed to generate interrupts on regular intervals or can be used to implement delay functionality. The RECON-IO module supports digital output, PWM with programmable frequency.

Coming together with the hardware is the scripts (resided in the sw folder) that allow you to:

– Quickly generate a bsp from the sopc file.

– Quickly generate library that supports some “Arduino” style functions such as delay, digitalWrite, digitalRead …

– Quickly generate a new application

Examples are provided to demonstrate and test the “shipped” platform.



This article has 2 comments

  1. I am a beginner of FPGA. Now,I am practicing how to use QuartusPrime web edition. My goal is to output ADC data of max 1000 and logic analyzer data to UART.
    I was impressed with your article.
    However, an error occurs and Platform Designer can not generate HDL.

    Error: recon_0a.recon_io_1: Component recon_io 1.0 not found or could not be instantiated
    Error: recon_0a.recon_timer_1: Component recon_timer 1.0 not found or could not be instantiated

    Could you tell us how to install and use recon project for beginners?


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