Turn your FPGA Devkit into a logic analyzer – a logic analyzer below $30

Any cheap FPGA development kit can be turned into a logic analyzer pretty easily with just a few steps. If you’re looking for an affordable and legitimate logic analyzer to debug simple stuff such as Serial/I2C/SPI interface, you can make one your own by purchasing a small FPGA kit (such as this one: MAX1000) and convert it into a logic analyzer. However, you have to be extra careful of what voltage level that you’re connecting to and some FPGA IOs are quite sensitive to voltage overshooting/undershooting/ESD strikes etc.

Below is a picture of the hardware of our FPGA-based logic analyzer. It depends on your development kit, you may or may not need to design a front end circuit to protect your FPGA IOs and convert the signals to appropriate level. In my example here, the front-end is a simple voltage divider so that I can probe 5-V output of the Arduino.  The Arduino generates a 1kHz square wave on digital pin 2. Because Arduino output is 5-V signal, I use a voltage divider to divide the voltage from 5V to 2.5V. The voltage divider is made of tw0 470kOhm in series which gives an impedance of almost 1M. In this example, I use BeMicroMAX10 board which has sadly been discontinued but you can use any board. The colorful cable is an 10-way jumper wire. 8 of the wires are used for signals, 2 are for GND.

Firmware design: very simple. In fact, this is all it has

Here’s how it works:

  • Intel Quartus software already includes a logic analyzer user interface and logic block which captures and stores digital signals in a buffer and uploads to Host PC via USB-JTAG interface. This block is the sigtal_tap_u0 block in the source code. This tool allows you to do pre/post-trigger.
  • We need a way to change sampling time depending on the signals we wish to observe. This is done by using a timer whose period can be controlled from host PC. The timer runs and restarts when it reaches the period, and generates a pulse which is our sampling clock. The period of the sampling pulses is controlled by Quartus’ “In-system source/probe” tool.
  • And … nothing else. This is a basic setup. With programmable device, you can change the firmware to do more fancy stuff, for example protocol decoder or sequence detector.

Host PC Software: nothing do be done. All FPGA vendors have decent Logic analyzer for debugging. Let’s just use theirs. This is how it looks like in Quartus Signal Tap logic analyzer. For Xilinx, you can use Chipscope or Vivado Debug Hub.

To control the sampling period, a second GUI tool is required (I know it’s not ideal but it’s not the end of the world). Again, Xilinx has Virtual IO tool which lets you probe and drive slow signals internal to the FPGA. Note that the period is calculated as follow:

Sampling Period = Clock_Period * (SET_VALUE + 1).


Visit this site for the project and source code.



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